iverilog
Port variant standard
Summary Verilog simulation and synthesis tool
Package version 10.3_1
Homepage http://iverilog.icarus.com/
Keywords cad
Maintainer Michael Neumann
License GPLv2+
Other variants There are no other variants.
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Last modified 22 DEC 2019, 20:24:28 UTC
Port created 07 JAN 2018, 18:28:25 UTC
Subpackage Descriptions
single Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-2000. The standard proper is due to be release towards the middle of the year 2000. This is a fairly large and complex standard, so it will take some time for it to get there, but that's the goal.
Configuration Switches (platform-specific settings discarded)
This port has no build options.
Package Dependencies by Type
Build (only) gperf:single:standard
gmake:single:standard
autoconf:single:standard
automake:single:standard
bison:primary:standard
Build and Runtime readline:single:standard
Runtime (only) gcc9:cxx_run:standard (single subpackage)
Download groups
main mirror://GITHUB/steveicarus:iverilog:v10_3
Distribution File Information
4b884261645a73b37467242d6ae69264fdde2e7c4c15b245d902531efaaeb234 1600835 steveicarus-iverilog-10_3.tar.gz
Ports that require iverilog:standard
No other ports depend on this one.