||Icarus Verilog is a Verilog simulation and synthesis tool. It
operates as a compiler, compiling source code written in Verilog
(IEEE-1364) into some target format. For batch simulation, the
compiler can generate C++ code that is compiled and linked with
a run time library (called "vvm") then executed as a command to
run the simulation. For synthesis, the compiler generates netlists
in the desired format.
The compiler proper is intended to parse and elaborate design
descriptions written to the IEEE standard IEEE Std 1364-2000. The
standard proper is due to be release towards the middle of the
year 2000. This is a fairly large and complex standard, so it will
take some time for it to get there, but that's the goal.
Configuration Switches (platform-specific settings discarded)
This port has no build options.
Package Dependencies by Type
Distribution File Information
4b884261645a73b37467242d6ae69264fdde2e7c4c15b245d902531efaaeb234 1600835 steveicarus-iverilog-10_3.tar.gz
Ports that require iverilog:standard
|No other ports depend on this one.|