Port variant standard
Summary Verilog simulation and synthesis tool
Package version 12.0
Homepage http://iverilog.icarus.com/
Keywords cad
Maintainer Michael Neumann
License GPLv2+
Other variants There are no other variants.
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Last modified 02 JAN 2023, 22:26:52 UTC
Port created 07 JAN 2018, 18:28:25 UTC
Subpackage Descriptions
single Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-2000. The standard proper is due to be release towards the middle of the year 2000. This is a fairly large and complex standard, so it will take some time for it to get there, but that's the goal.
Configuration Switches (platform-specific settings discarded)
This port has no build options.
Package Dependencies by Type
Build (only) gperf:primary:standard
Build and Runtime readline:primary:standard
Runtime (only) ravensys-gcc:cxx_run:standard (single subpackage)
ravensys-gcc:libs:standard (single subpackage)
Download groups
main mirror://GITHUB/steveicarus:iverilog:v12_0
Distribution File Information
a68cb1ef7c017ef090ebedb2bc3e39ef90ecc70a3400afb4aa94303bc3beaa7d 2995096 steveicarus-iverilog-12_0.tar.gz
Ports that require iverilog:standard
No other ports depend on this one.