Ravenport: iverilog

Port variant	std
Summary	Verilog simulation and synthesis tool
BROKEN
Package version	12.0_1
Homepage	http://iverilog.icarus.com/
Keywords	cad
Maintainer	Michael Neumann
License	GPLv2+
Other variants	There are no other variants.
Ravenports	Buildsheet \| History
Ravensource	Port Directory \| History
Last modified	11 AUG 2024, 22:51:45 UTC
Port created	07 JAN 2018, 18:28:25 UTC

Subpackage Descriptions

set	Subpackage description undefined (port maintainer error).
primary	Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-2000. The standard proper is due to be release towards the middle of the year 2000. This is a fairly large and complex standard, so it will take some time for it to get there, but that's the goal.
dev	This is the developer subpackage of the iverilog:std port. It may contain headers, pc files, static and PIC libraries and SO links.
man	This is the man page subpackage of the iverilog:std port.

Build (only)	gperf:primary:std gmake:primary:std readline:dev:std autoconf:primary:std automake:primary:std bison:primary:std
Build and Runtime	readline:primary:std
Runtime (only)	ravensys-gcc:cxx_run:std (primary subpackage) ravensys-gcc:libs:std (primary subpackage)